-- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity VDGMEMCNT is port ( A : in std_logic_vector(15 downto 0); D : in std_logic_vector(7 downto 0); BUSACKN : in std_logic; VRAMSW1 : in std_logic; CGSELN : in std_logic; CRTKILLN : in std_logic; CLK14M : in std_logic; RSTN : in std_logic; AOUT : out std_logic_vector(13 downto 0); AOUT_ENBN : out std_logic; DOUT : out std_logic_vector(7 downto 0); DOUT_ENBN : out std_logic; BUSRQN : out std_logic; VCASN : out std_logic; VRASN : out std_logic; DISPD : out std_logic_vector(3 downto 0); DISPMD : out std_logic_vector(3 downto 0); DISPTMG_LT : out std_logic; -- display data latch pulse DISPTMG_DT : out std_logic; -- display data (256 x 192) DISPTMG_BD : out std_logic; -- display data and border (320 x 240) DISPTMG_HS : out std_logic; -- horizontal sync pulse DISPTMG_VS : out std_logic -- vertical sync pulse ); end VDGMEMCNT; architecture RTL of VDGMEMCNT is signal mca : std_logic_vector(12 downto 0); signal mcd : std_logic_vector(7 downto 0); signal hsn : std_logic; signal hsn_f1 : std_logic; signal fsn : std_logic; signal rpn : std_logic; signal maintmgcnt : std_logic_vector(3 downto 0); signal vcasmskn : std_logic; signal mca_sel : std_logic; signal mca_mux : std_logic_vector(3 downto 0); signal lah : std_logic_vector(7 downto 0); signal att : std_logic_vector(7 downto 0); signal mskvcnt : std_logic_vector(11 downto 0); signal mskhcnt : std_logic_vector(11 downto 0); signal mskv : std_logic; signal mskh : std_logic; signal busrqwdn : std_logic; signal cgadcnt : std_logic_vector(3 downto 0); signal aclr : std_logic; signal cromad : std_logic_vector(11 downto 0); signal cromdt : std_logic_vector(7 downto 0); signal aout_i : std_logic_vector(13 downto 0); signal aout_enb : std_logic; signal aout_enbn_i : std_logic; signal dout_i : std_logic_vector(7 downto 0); signal dout_enbn_i : std_logic; signal busrqn_i : std_logic; signal vcasn_i : std_logic; signal vrasn_i : std_logic; signal vrasn_f1 : std_logic; component MC6847 is port ( D : in std_logic_vector(7 downto 0); MSN : in std_logic; AN_G : in std_logic; AN_S : in std_logic; INTN_EXT : in std_logic; GM0 : in std_logic; GM1 : in std_logic; GM2 : in std_logic; CSS : in std_logic; INV : in std_logic; CLK14M : in std_logic; RSTN : in std_logic; A : out std_logic_vector(12 downto 0); FSN : out std_logic; HSN : out std_logic; RPN : out std_logic; Y : out std_logic_vector(5 downto 0); C_A : out std_logic_vector(3 downto 0); C_B : out std_logic_vector(2 downto 0); DISPD : out std_logic_vector(3 downto 0); DISPMD : out std_logic_vector(3 downto 0); DISPTMG_LT : out std_logic; -- display data latch pulse DISPTMG_DT : out std_logic; -- display data (256 x 192) DISPTMG_BD : out std_logic; -- display data and border (320 x 240) DISPTMG_HS : out std_logic; -- horizontal sync pulse DISPTMG_VS : out std_logic; -- vertical sync pulse HCNT : out std_logic_vector(9 downto 0) ); end component; component CGROM60 is port ( aclr : in std_logic; address : in std_logic_vector(11 downto 0); clock : in std_logic; q : out std_logic_vector(7 downto 0) ); end component; begin U_MC6847 : MC6847 port map ( D => mcd, MSN => aout_enb, AN_G => att(7), AN_S => att(6), INTN_EXT => att(5), GM0 => att(4), GM1 => att(3), GM2 => att(2), CSS => att(1), INV => att(0), CLK14M => CLK14M, RSTN => RSTN, A => mca, FSN => fsn, HSN => hsn, RPN => rpn, Y => open, C_A => open, C_B => open, DISPD => DISPD, DISPMD => DISPMD, DISPTMG_LT => DISPTMG_LT, DISPTMG_DT => DISPTMG_DT, DISPTMG_BD => DISPTMG_BD, DISPTMG_HS => DISPTMG_HS, DISPTMG_VS => DISPTMG_VS, HCNT => open ); -- hsn delay process (CLK14M,RSTN) begin if (RSTN = '0') then hsn_f1 <= '1'; elsif (CLK14M'event and CLK14M = '1') then hsn_f1 <= hsn; end if; end process; -- main timing counter process (CLK14M,RSTN) begin if (RSTN = '0') then maintmgcnt <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (hsn = '0') then maintmgcnt <= "0001"; else maintmgcnt <= maintmgcnt + 1; end if; end if; end process; process (CLK14M,RSTN) begin if (RSTN = '0') then aout_enb <= '0'; elsif (CLK14M'event and CLK14M = '1') then if (maintmgcnt = "1111") then if (busrqwdn = '0' and BUSACKN = '0') then aout_enb <= '1'; else aout_enb <= '0'; end if; end if; end if; end process; aout_enbn_i <= not aout_enb; process (CLK14M,RSTN) begin if (RSTN = '0') then vcasmskn <= '1'; elsif (CLK14M'event and CLK14M = '1') then if (maintmgcnt = "0111") then vcasmskn <= aout_enbn_i; end if; end if; end process; vcasn_i <= '0' when (vcasmskn = '0' and maintmgcnt(3) = '1' and maintmgcnt(1) = '1') else '1'; vrasn_i <= '0' when (vcasn_i = '0' or (aout_enb = '1' and maintmgcnt(3) = '1')) else '1'; -- Data latch process (CLK14M,RSTN) begin if (RSTN = '0') then lah <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (maintmgcnt = "1100") then lah <= D; end if; end if; end process; process (CLK14M,RSTN) begin if (RSTN = '0') then vrasn_f1 <= '1'; elsif (CLK14M'event and CLK14M = '1') then vrasn_f1 <= vrasn_i; end if; end process; process (CLK14M,RSTN) begin if (RSTN = '0') then att <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (vrasn_i = '1' and vrasn_f1 = '0') then att <= D; end if; end if; end process; -- address output process (CLK14M,RSTN) begin if (RSTN = '0') then mca_sel <= '0'; elsif (CLK14M'event and CLK14M = '1') then mca_sel <= maintmgcnt(2); end if; end process; mca_mux <= (mca(12 downto 9) + 1) when (mca_sel = '0') else "0000"; process (CLK14M,RSTN) begin if (RSTN = '0') then aout_i <= (others => '1'); elsif (CLK14M'event and CLK14M = '1') then if (aout_enbn_i = '0') then aout_i <= VRAMSW1 & mca_mux & mca(8 downto 0); else aout_i <= (others => '1'); end if; end if; end process; -- bus request -- vertical counter process (CLK14M,RSTN) begin if (RSTN = '0') then mskvcnt <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (fsn = '0') then mskvcnt <= (others => '0'); elsif (hsn = '0' and hsn_f1 = '1') then mskvcnt <= mskvcnt + 1; end if; end if; end process; process (CLK14M,RSTN) begin if (RSTN = '0') then mskv <= '0'; elsif (CLK14M'event and CLK14M = '1') then if (fsn = '0') then mskv <= '0'; elsif (mskvcnt(5 downto 0) = "100110") then mskv <= '1'; end if; end if; end process; -- horizontal counter process (CLK14M,RSTN) begin if (RSTN = '0') then mskhcnt <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (hsn = '0') then mskhcnt <= (others => '0'); elsif (maintmgcnt = "0111") then mskhcnt <= mskhcnt + 1; end if; end if; end process; process (CLK14M,RSTN) begin if (RSTN = '0') then mskh <= '0'; elsif (CLK14M'event and CLK14M = '1') then if (hsn = '0') then mskh <= '0'; elsif (mskhcnt(5 downto 0) = "000111") then mskh <= '1'; elsif (mskhcnt(5 downto 0) = "101100") then mskh <= '0'; end if; end if; end process; busrqwdn <= '0' when (CRTKILLN = '1' and mskv = '1' and mskh = '1') else '1'; process (CLK14M,RSTN) begin if (RSTN = '0') then busrqn_i <= '1'; elsif (CLK14M'event and CLK14M = '1') then if (maintmgcnt = "1111") then busrqn_i <= busrqwdn; end if; end if; end process; -- cgrom address process (CLK14M,RSTN) begin if (RSTN = '0') then cgadcnt <= (others => '0'); elsif (CLK14M'event and CLK14M = '1') then if (rpn = '0') then cgadcnt <= (others => '0'); elsif (hsn = '1' and hsn_f1 = '0') then if (fsn = '0') then cgadcnt <= "1001"; else cgadcnt <= cgadcnt + 1; end if; end if; end if; end process; aclr <= not RSTN; U_CGROM60 : CGROM60 port map ( aclr => aclr, address => cromad, clock => CLK14M, q => cromdt ); cromad <= A(11 downto 0) when (BUSACKN = '1') else lah & cgadcnt; dout_i <= cromdt when (CGSELN = '0') else (others => '1'); dout_enbn_i <= CGSELN; mcd <= cromdt when (att(6) = '0' and att(5) = '1') else lah; AOUT <= aout_i; AOUT_ENBN <= aout_enbn_i; DOUT <= dout_i; DOUT_ENBN <= dout_enbn_i; BUSRQN <= busrqn_i; VCASN <= vcasn_i; VRASN <= vrasn_i; end RTL;